The invention relates to a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells. In particular, one embodiment of the invention relates to CBRAM resistance elements. An exemplary resistive memory arrangement is disclosed in WO 03/098636 A2. Hitherto, the memory cells of a resistive memory arrangement have been structured either in the form of a cross-point array (cf. accompanying FIG. 10) or in a 1T1R arrangement (cf. FIG. 11). FIG. 11 illustrates that each resistive memory element Rc is assigned precisely one selection or drive element T, in this case a FET, for the selection of the memory element. In the case of this circuit arrangement, the control electrode of the drive transistor T is connected to a word line WL running in the column direction and one controlled electrode of said transistor is connected to a bit line BL running in the row direction. The other controlled electrode of the drive transistor T is connected to one electrode of a CBRAM resistance element Rc, the other electrode of which is connected to a plate line PL.
WO 03/098636 A2 illustrates a possibility for combining both circuit arrangements. A further proposal for NRAM memories is set forth in WO 02/084705 A2. In the case of the memory arrangement described in the latter document, all resistance elements are connected up only to one line. The write lines are used for addressing the different resistors. Disadvantages of the cross-point arrangement in accordance with FIG. 10 are the restricted size of the memory array, the complicated read-out of the stored values and the associated delay of the read-out value. The 1T1R cell illustrated in FIG. 11 can be read faster and in a less complicated manner, but its space requirement is higher. A first compromise is the solution described in WO 03/098636 A2, in which smaller cross-point arrangements are connected up (arranged vertically). The main emphasis of this compromise is placed on the smaller space requirement which is effected at the expense of speed. The solution proposed in WO 02/084705 A2 is slow on account of two read cycles and, since a write line is used, is suitable only for MRAM memory arrangements.